You do a test in Q1 and see what succeeds with you from the 4 data in the table, and in Q2 you choose the one who succeeded with you, then you see the data of the one who succeeded with you, it becomes stage 1, or stage 2, or 3. for example, If it is a stage 1, fill the stage 1 table, and leave Stage 2 and 3.

Stage II: O CE O CC R= R = Ar Rg = RX = Q1. For the following cases, suggest the appropriate cascaded stages of CE's and CC's: # R. r. Configuration 1 2 3k s 100 2 2 25k_2 10 60092 3 2 302 s 2002 10 4 2 250 s 200 100 A. = R= Soon Stage III: OCE OCC R = RE Rg = RX- Q2. Design one of the cases above given Vee = 15, B = 120 and Icmar = 10mA. The source and load are Rs = 2K and R = 8k12. A = R = Design for Case # 0 10 20 30 4 Q3. Simulate the design and report the percentage error in the total voltage gain. Stages: Stage 1: Re- o CC R. = A. Simulator = Error Percentage R = Rx = A = R = Bonus Assignment circuit schematic circuit simulation: Stage II: O CE O CC R= R = Ar Rg = RX = Q1. For the following cases, suggest the appropriate cascaded stages of CE's and CC's: # R. r. Configuration 1 2 3k s 100 2 2 25k_2 10 60092 3 2 302 s 2002 10 4 2 250 s 200 100 A. = R= Soon Stage III: OCE OCC R = RE Rg = RX- Q2. Design one of the cases above given Vee = 15, B = 120 and Icmar = 10mA. The source and load are Rs = 2K and R = 8k12. A = R = Design for Case # 0 10 20 30 4 Q3. Simulate the design and report the percentage error in the total voltage gain. Stages: Stage 1: Re- o CC R. = A. Simulator = Error Percentage R = Rx = A = R = Bonus Assignment circuit schematic circuit simulation