You have a FET made of pristine (undoped) Si with a SiO2 insulating layer. Assume that the thickness of SiO2 (the gate dielectric) is dox = 300 nm. You also know that about 1 out of 100 Si atoms at the Sis surface at the interface is a defect site that works as a deep electron trap (traps one electron per site). The electron mobility, the channel length and width are also known: e = 103 cm2V-1s-1, L = 1 mm, and W = 1 mm, respectively. The dielectric constant of SiO2 is = 4, and the lattice constant of Si is 5.43 .

(a) Determine the source-drain current, ISD, that would be flowing through the FET, when a gate voltage of VG = +92 V and a source-drain voltage of VSD = +1 V are applied. Assume that the contact resistance is negligible. Give your answer for the current in A. Be careful with the units (convert nm, mm and cm to m).

(b) What is the smallest VG, at which a non-zero current ISD would start flowing through this FET?