You have to design a finite state machines (FSM) diagram to read serial bit stream and to generate output if below condition has occurred. 1. Light up led_1 if you detect more than 1 occurring of 10101110 pattern. 2. Blink led_1 if you detect more than 2 occurring of 10101110 pattern at a rate of 1s. 3. Light up led_2 if you detect more than 4 occurring of 101 pattern. 4. Blink led_2 if you detect more than 7 occurring of 101 pattern at a rate of 1s. * Pattern can be overlapped * Designs the Mealy FSM *You have to submit the FSM diagram and verilog code only to implement the FSM diagram which you have drawn (you can assume AXI4-S data input)