Your answers to these problems should contain explanations of the computations and calculations. If you make additional assumptions, state them explicitly and provide justifications for them. 1. The function L is defined as L(1) = 2, L(2) = 1, L(3) = 3, L(4) = 4 and for n > 4, L(n) + L(n 1)+L(n 2) L(n + 1) = L(n 3) i.e., the (n+1)-th value is given by the sum of the n-th, n - 1-th and n - 2-th values divided by the n - 3-th value. (a) Write an assembly program for computing the k-th value L(k), where k is an integer bigger than 4 read from a memory location M, and storing L(k) at memory location M. Use the instruction set in the Instruction Set Architecture document (b) Consider a pipelined processor, where the pipeline stages are IF (instruction fetch), ID (instruction decode), RR (register read), EX (execute instruction), WB (write back result into register).. Describe what happens in the pipeline stages for the various types (data movement, data processing, control) of instructions. (c) Show the execution of your program on the above pipelined pro- cessor for k = 6 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with unlimited capacity (you can store any number of instruc- tions in the IW). Explain where and why delay slots appear. Instruction Set Architecture We present a list of instructions typical of a RISC (reduced set instruction computer) machine. In data-movement and control instructions, the addresses may be immediate #x, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. PC is the program counter and a 4, L(n) + L(n 1)+L(n 2) L(n + 1) = L(n 3) i.e., the (n+1)-th value is given by the sum of the n-th, n - 1-th and n - 2-th values divided by the n - 3-th value. (a) Write an assembly program for computing the k-th value L(k), where k is an integer bigger than 4 read from a memory location M, and storing L(k) at memory location M. Use the instruction set in the Instruction Set Architecture document (b) Consider a pipelined processor, where the pipeline stages are IF (instruction fetch), ID (instruction decode), RR (register read), EX (execute instruction), WB (write back result into register).. Describe what happens in the pipeline stages for the various types (data movement, data processing, control) of instructions. (c) Show the execution of your program on the above pipelined pro- cessor for k = 6 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with unlimited capacity (you can store any number of instruc- tions in the IW). Explain where and why delay slots appear. Instruction Set Architecture We present a list of instructions typical of a RISC (reduced set instruction computer) machine. In data-movement and control instructions, the addresses may be immediate #x, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. PC is the program counter and a
