Your system, running at 2GHz has the following instruction mix, with CPI that doesn't include memory accesses. The main memory has an access latency of 50 ns, and the cache may be accessed within a single stage in the pipeline with no penalty Instruction ALU Branch Load Store Frequency | 55% | 10% | 22% | 13% CPI The cache performance metrics are as follows: I-cache miss rate D-cache miss rate Fraction of dirty D-cache lines (for write-back cache) 5% 10% 25% (a) What is the overall CPI, excluding memory access penalties? (b) What is the average access time for the I-cache? What is the penalty to overall CPI from misses in the I-cache? (c) What is the average access time for the D-cache? What is the penalty to overall CPI from misses in the D-cache? Ignore any delays due to writes. (d) In reality, writes do cause delays. Assuming a write-through cache, the memory system must slow down to accommodate all of the writes that the CPU issues. How many instructions are issued in 100 ns, assuming no other cache misses (we've already paid for those separately)? How many of those are y are generated as a result of those store instructions, and how long do they actually take? What is the resulting penalty to CPI? You can compute this by subtracting 100 ns stores? How many writes to memor from the time that the resulting writes actually take. access time for this D-cache, and the resulting penalty to CPI CPI metrics. How much faster will the resulting system run? Assume the system from Problem 3e (e) Based on your results from 3d, you realize that you need a write-back cache. Compute the average data (f) Your CPU designer says that she can increase the clock frequency to 2.5 GHz, without impacting the