Consider the FSM H = of Figure 10.50, where S = {A,B,C,D,E, F,G} is the set of states, I = {ri,

a, c, x, z} is the set of inputs, O = {null,

b, f, d} is the set of outputs, A is the initial state,

δ : S × I → S is the next-state function, and λ : S × I → O is the output function.

(a) Generate UIO sequence(s) for each state of the FSM, if those exist.

(b) Generate test sequences for each transition of the FSM using UIO sequences for state verification. Assume that a reset input ri will always bring the FSM back to its initial state A. The FSM produces a null output in response to the ri input.

(c) Represent the following two test cases in TTCN-3 form with verdicts:

(B,C, c/d) and (A,B, a/b).