A low-power TTL logic gate with an active pnp pull-up device is shown in Figure P17.35. The

Question:

A low-power TTL logic gate with an active pnp pull-up device is shown in Figure P17.35. The transistor parameters are \(\beta_{F}=100\) and \(\beta_{R}=0.2\) (for each input emitter). Assume a fanout of 5.

(a) For \(v_{X}=v_{Y}=v_{Z}=0.1 \mathrm{~V}\), determine \(i_{B 1}, i_{B 2}, i_{B 3}, i_{C 2}\), and \(i_{C 3}\).

(b) Repeat part (a) for \(v_{X}=v_{Y}=\) \(v_{Z}=2 \mathrm{~V}\).

image text in transcribed

Fantastic news! We've Found the answer you've been seeking!

Step by Step Answer:

Related Book For  book-img-for-question
Question Posted: