Consider the basic diff-amp with active load and current biasing in Figure 13.14. Using the parameters and results of Example 13.8, determine the maximum range of common-mode input voltage under the conditions that the minimum source-to-drain voltage for a PMOS is limited to \(v_{S D}(\mathrm{~min})=v_{S D}(\mathrm{sat})+0.2 \mathrm{~V}\) and the minimum drain-to-source voltage for an NMOS is limited to \(v_{D S}(\mathrm{~min})=v_{D S}(\mathrm{sat})+0.2 \mathrm{~V}\).

Data From Example 13.8:-

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30 Mg M5 M6 Iset www M M2 C M Rsel M4 M3 Figure 13.14 MC14573 CMOS op-amp equivalent circuit