Consider the BiFET differential input stage in Figure P13.61, biased with power supply voltages \(V^{+}\)and \(V^{-}\). Let \(V^{+}=-V^{-} \equiv V_{S}\).

(a) Design the bias circuit such that \(I_{\mathrm{REF} 2}=100 \mu \mathrm{A}\) for supply voltages in the range \(3 \leq V_{S} \leq 12 \mathrm{~V}\). Determine \(V_{Z K}, R_{3}\), and the JFET parameters.

(b) Determine the value of \(R_{4}\) such that \(I_{O 1}=500 \mu \mathrm{A}\) when \(V^{+}=12 \mathrm{~V}\).

Transcribed Image Text:

20 Qi ICA Q2 JFET input Incremental current mirror TRI=1 23 www QA Figure P13.61 pair QD www 1C4 Rload 24 102 QB Bias for QA ww R pnp current ww out mirror QE IREFI RA Bias for. Zener D Vout R3 + REF2 D VDI DVZK V-