Enhancement-mode NMOS and PMOS devices both have parameters (L=4 mu mathrm{m}) and (t_{mathrm{ox}}=500 ). For the NMOS

Enhancement-mode NMOS and PMOS devices both have parameters \(L=4 \mu \mathrm{m}\) and \(t_{\mathrm{ox}}=500 Å\). For the NMOS transistor, \(V_{T N}=+0.6 \mathrm{~V}\), \(\mu_{n}=675 \mathrm{~cm}^{2} / \mathrm{V}-\mathrm{s}\), and the channel width is \(W_{n}\); for the PMOS transistor, \(V_{T P}=-0.6 \mathrm{~V}, \mu_{p}=375 \mathrm{~cm}^{2} / \mathrm{V}-\mathrm{s}\), and the channel width is \(W_{p}\). Design the widths of the two transistors such that they are electrically equivalent and the drain current in the PMOS transistor is \(I_{D}=0.8 \mathrm{~mA}\) when it is biased in the saturation region at \(V_{S G}=5 \mathrm{~V}\). What are the values of \(K_{n}, K_{p}\), \(W_{n}\), and \(W_{p}\) ?