For the two-input NMOS NOR logic gate in Figure 3.46 in the text, the transistor parameters are \(V_{T N 1}=V_{T N 2}=0.6 \mathrm{~V}, \lambda_{1}=\lambda_{2}=0\), and \(k_{n 1}^{\prime}=k_{n 2}^{\prime}=\) \(120 \mu \mathrm{A} / \mathrm{V}^{2}\). The drain resistor is \(R_{D}=50 \mathrm{k} \Omega\).

(a) Determine the width-tolength ratios of the transistors so that \(V_{O}=0.15 \mathrm{~V}\) when \(V_{1}=V_{2}=5 \mathrm{~V}\). Assume that \((W / L)_{1}=(W / L)_{2}\).

(b) Using the results of part (a), find \(V_{O}\) when \(V_{1}=5 \mathrm{~V}\) and \(V_{2}=0.2 \mathrm{~V}\).

Figure 3.46:-

Transcribed Image Text:

VDD=5V IR RD IDI M V2 1 - Vo ID2 M Figure 3.46 A two-input NMOS NOR logic gate