The circuit in Figure P10.56 is a PMOS version of a two-transistor MOS current mirror. Assume transistor

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The circuit in Figure P10.56 is a PMOS version of a two-transistor MOS current mirror. Assume transistor parameters of \(V_{T P}=-0.4 \mathrm{~V}\), \(k_{p}^{\prime}=60 \mu \mathrm{A} / \mathrm{V}^{2}\), and \(\lambda=0\). The transistor width-to-length ratios are \((W / L)_{1}=25,(W / L)_{2}=15\), and \((W / L)_{3}=5\).

(a) Determine \(I_{O}, I_{\mathrm{REF}}\), \(V_{S G 1}\), and \(V_{S G 3}\).

(b) What is the largest value of \(R\) such that \(M_{2}\) remains biased in the saturation region?

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