The enhancement-load transistor in the NMOS inverter in Figure P16.8 has a separate bias applied to the gate. Assume transistor parameters of \(K_{n}=1 \mathrm{~mA} / \mathrm{V}^{2}\) for \(M_{D}, K_{n}=0.4 \mathrm{~mA} / \mathrm{V}^{2}\) for \(M_{L}\), and \(V_{T N}=1 \mathrm{~V}\) for both transistors. Using the appropriate logic 0 and logic 1 input voltages, determine \(V_{O H}\) and \(V_{O L}\) for:

(a) \(V_{B}=4 \mathrm{~V}\),

(b) \(V_{B}=5 \mathrm{~V}\),

(c) \(V_{B}=6 \mathrm{~V}\), and

(d) \(V_{B}=7 \mathrm{~V}\).

Transcribed Image Text:

VB VDD = 5 V ML Figure P16.8 MD Ovo