A RISC machine may do both a mapping of symbolic registers to actual registers and a rearrangement of instructions for pipeline efficiency. An interesting question arises as to the order in which these two operations should be done. Consider the following program fragment:

a. First do the register mapping and then any possible instruction reordering. How many machine registers are used? Has there been any pipeline improvement?
b. Starting with the original program, now do instruction reordering and then any possible mapping. How many machine registers are used? Has there been any pipeline improvement?

LD SR1,A LD SR2, B ADD SR3, SR1, SR2 add contents of SR1 and SR2 and store in SR3 LD SR4, C LD SR5, D ADD SR6, SR4. SR5 load A into symbolic register 1 load B into symbolic register2