Assuming that the zero has been moved to infinity, determine the maximum load capacitance that can be attached directly to the output of the circuit of Fig. 9.60 and still maintain a phase margin of 45°. Neglect all higher order poles except any due to the load capacitance. Use the value of W/L obtained in Problem 9.23 for M₉with the bias circuit of Fig. 9.61.

Fig. 9.60:

Fig. 9.61:

Transcribed Image Text:

+5 V Mg M5 100 M, 100 100 Vi м. M2 100 100 Vo 5 pF 20 μΑ (1) M9 100 M6 50 50 Мз -5 V +5 V Mg 100 M40 100 8. M41 100 1O 20 µA M42 100 8. Mg -5 V