Repeat Problem 4.38 but replace the bipolar transistors with MOS transistors as in Problem 4.14. Assume the worst-case W/L mismatches in the transistors are ± 5 percent and the worst-case V_tmismatches are ± 10 mV. Assume the dc output voltage to ground is V_SUPˆ’ |V_GS3|. Also, assume.

Data from Prob. 4.38:

Determine the worst-case input offset voltage for the circuit of Fig. 4.58. Assume the worst-case I_S mismatches in the transistors are ± 5 percent and β_F = 15 for the pnp transistors. Assume the dc output voltage is V_SUP ˆ’ |V_BE(on)|.

Fig. 4.58:

Transcribed Image Text:

+VSUP Q4 Q3 V, = Vo+v, Q2 +6 V; = V, + v; 100 μΑ -VSUP