What modifications would have to be made to the architecture of the computer in Figure P7.12 to implement predicated execution like the ARM? 

FIGURE P7.12 PC_MPLX 00 014 10 11 BRA Target where the target address is [PC]+4+4 L MPLX BRA Target PC 0 Z PC_MPLX control PC Branch Jump Architecture of a hypothetical computer PC address Instruction Memory PC_adder PC data 32-bit branch target address 4 Opcode Literal L + Branch_adder The Z-bit from the CCR controls the PC multiplexer. It selects between next address and branch address. Register file S1 address S2 address Daddress Ddata S1 data S2 data Sign extension Left shift x 2 ALU_MPLX 0 32-bit sign-extended byte offset MPLX S1 data ALU S2data Load data 32-bit sign-extended word offset Memory address Data memory Maddress Mdata out Mdata in Memory MPLX 0 MPLX Cengage Leaming 2014