What modifications would have to be made to the architecture of the computer in Figure P7.12 to implement operand shifting ( as part of a normal instruction) like the ARM? 

FIGURE P7.12 PC_MPLX 00 01 BRA Target where the target address is [PC]+4+4*L MPLX 10 11 PC Jump 0 Z PC_MPLX control BRA Target PC Branch Architecture of a hypothetical computer PCaddress Instruction Memory PC adder PC data 32-bit branch target address 4 Opcode FU Literal L Branch_adder The Z-bit from the CCR controls the PC multiplexer. It selects between next address and branch address. Register file S1 address S2 address Daddress Ddata S1 data S2 data Sign extension Left shift x 2 ALU_MPLX To MPLX 32-bit sign-extended byte offset $1 data Load data 32-bit sign-extended word offset ALU S2 data Memory address Data memory Maddress Mdata out Mdata in Memory_MPLX 0 MPLX Cengage Leaming 2014 )