Question: You are redesigning an existing RISC-style pipelined processor to make it a three-way superscalar processor that permits three instructions to be executed at the same

You are redesigning an existing RISC-style pipelined processor to make it a three-way superscalar processor that permits three instructions to be executed at the same time.

a. Do you expect the new processor to achieve three instructions per clock?

b. What level of design complexity do you expect the new processor to have in comparison with the pipelined version?

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