Cache block size (B) can affect both miss rate and miss latency. Assuming a 1-CPI machine

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Cache block size (B) can affect both miss rate and miss latency. Assuming a 1-CPI machine with an average of 1.35 references (both instruction and data) per instruction, help find the optimal block size given the following miss rates for various block sizes.

8: 4% 16:3% 32: 2% 64: 1.5% 128: 1%


1. What is the optimal block size for a miss latency of 20 × B cycles?
2. What is the optimal block size for a miss latency of 24 + B cycles?
3. For constant miss latency, what is the optimal block size?

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