Assume that we already have a single-cycle design. How many bits in total do we need for pipeline registers to implement the pipelined design?

This exercise explores some of the tradeoffs involved in pipelining, such as clock cycle time and utilization of hardware resources. The first three problems in this exercise refer to the following MIPS code. The code is written with an assumption that the processor does not use delay slots.

a. b. SW R16,-100 (R6) LW R16,8(R6) BEQ R5, R4, Label; Assume R5 != R4 ADD R5, R16, R4 SLT R5, R15, R4 OR R1, R2, R3 SW R1,0 (R2) BEQ R1, RO, Label; Assume R1 OR R2, R1, RO Label: ADD R1, R1, R3 == RO