Consider the entire memory hierarchy. What kinds of optimizations can improve the number of concurrent misses?

Both Barcelona and Nehalem are chip multiprocessors (CMPs), having multiple cores and their caches on a single chip. CMP on-chip L2 cache design has interesting trade-offs. The following table shows the miss rates and hit latencies for two benchmarks with private vs. shared L2 cache designs. Assume L1 cache misses once every 32 instructions.

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Benchmark A misses-per-instruction Benchmark B misses-per-instruction Private 0.30% 0.06% Shared 0.12% 0.03%