Question: Given these latencies for individual elements of the datapath, compare clock cycle times of the single-cycle and the 5-stage pipelined datapath. The remaining three problems

Given these latencies for individual elements of the datapath, compare clock cycle times of the single-cycle and the 5-stage pipelined datapath.

The remaining three problems in this exercise assume that components of the datapath have the following latencies: a. 1-Mem Add Mux ALU 200ps 70ps 20ps 90ps 200ps 50ps 250ps b. 750ps Regs D-Mem Sign-Extend 90ps 250ps 15ps

a. 1-Mem Add Mux ALU 200ps 70ps 20ps 90ps 200ps 50ps 250ps b. 750ps Regs D-Mem Sign-Extend 90ps 250ps 15ps 300ps 500ps 100ps Shift-Left-2 10ps 5ps

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