If we use no forwarding, what fraction of cycles are we stalling due to data hazards?

This exercise is intended to help you understand the cost/complexity/performance trade-offs of forwarding in a pipelined processor. Problems in this exercise refer to pipelined datapaths from Figure 4.45. These problems assume that, of all the instructions executed in a processor, the following fraction of these instructions have a particular type of RAW data dependence. The type of RAW data dependence is identified by the stage that produces the result (EX or MEM) and the instruction that consumes the result (1st instruction that follows the one that produces the result, 2nd instruction that follows, or both). We assume that the register write is done in the first half of the clock cycle and that register reads are done in the second half of the cycle, so "EX to 3^rd" and "MEM to 3^rd" dependences are not counted because they cannot result in data hazards. Also, assume that the CPI of the processor is 1 if there are no data hazards.

Figure 4.45

Transcribed Image Text:

a. b. EX to 1st Only 5% 20% MEM to 1st Only 20% 10% EX to 2nd only 5% 15% MEM to 2nd Only 10% 10% EX to 1st and MEM to 2nd 10% 5% Other RAW Dependences 10% 0%