Questions and Answers of Essentials Of Computer Organization

A company that is selling database management optimization software contacts you to pitch its product. The representative claims that the memory management software will reduce page fault rates for
The execution times for three systems running five benchmarks are shown in the following table. Compare the relative performance of each of these systems (i.e., A to B, B to C, and A to C) using the
The execution times for three systems running five benchmarks are shown in the following table. Compare the relative performance of each of these systems (i.e., A to B, B to C, and A to C) using the
Use the FPGA illustrated below to implement a full adder.Label the outputs clearly. Draw lines between the cells to indicate a connection between the logic functions. X y Carry in
a) Show how a two-input XOR gate can be implemented in the PAL shown below.1.b) Show how a two-input NAND gate can be implemented in the PLA shown below. 1
Indicate whether each of the following applies to CISC or RISC by placing either a C (for CISC) or an R (for RISC) in the blank. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. execute. 1. Simple instructions
Given the following Omega network, which allows eight CPUs(P0 through P7) to access eight memory modules (M0 through M7):1.a) Show how the following connections through the network are achieved
39. If 800GB server-grade HDDs cost $300, electricity costs$0.10 per kilowatt hour, and facilities cost $0.01 per GB per month, use the disk specification in Figure 7.15 to determine how much it
17. The protocol for a certain data bus is shown in the table below.Draw the corresponding timing diagram. You may refer to Figure 7.11. Time Salient Bus Signal Meaning Assert to Bus is needed for
22. You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16
20. Suppose you have a byte-addressable virtual address memory system with eight virtual pages of 64 bytes each and four page frames. Assuming the following page table, answer the questions
19. Suppose a process page table contains the entries shown below. Using the format shown in Figure 6.22a, indicate where the process pages are located in memory 1 1 Frame Valid Bit 3 1 0 0 0
18. Suppose a process page table contains the entries shown below. Using the format shown in Figure 6.17a, indicate where the process pages are located in memory. Frame 1 Valid Bit 0 1 3 1 1 0 0 2 1
17. Redo exercise 16, assuming now that cache is 16-way set associative. Address OXOFFOFABA 0x00000011 OXOFFFFFFE 0x23456719 OXCAFEBABE TAG Cache Location (set) Offset Within Block
16. Assume a direct-mapped cache that holds 4096 bytes, in which each block is 16 bytes. Assuming that an address is 32 bits and that cache is initially empty, complete the table that follows.(You
12. 12. Given a byte-addressable memory with 256 bytes, suppose a memory dump yields the results shown below. The address of each memory cell is determined by its row and column. For example, memory
11. Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16-byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout
25. 25. Assuming the same stages as in Example 5.12, explain the potential pipeline hazards (if any) in each of the following code segments. X = R2+ Y 1. a) R4 R2+ X R1 = R2+ X X = R3+ Y 2. b) ZR1 + X
22. Suppose we have the instruction Load 500. Given that memory and register R1 contain the values below:and assuming that R1 is implied in the indexed addressing mode, determine the actual value
21. ◆21. Suppose we have the instruction Load 1000. Given that memory and register R1 contain the values below:and assuming that R1 is implied in the indexed addressing mode, determine the actual
16. 16.a) Write the following expression in postfix (reverse Polish)notation. Remember the rules of precedence for arithmetic operators!1.b) Write a program to evaluate the above arithmetic statement
5. 5. Consider a 32-bit hexadecimal number stored in memory as follows:1.a) If the machine is big endian and uses two’s complement representation for integers, write the 32-bit integer number
4. 4. Assume a computer that has 32-bit integers. Show how each of the following values would be stored sequentially in memory, starting at address 0x100, assuming that each address holds 1 byte.Be
3. 3. Fill in the following table to show how the given integers are represented, assuming that 16 bits are used to store values and the machine uses two’s complement notation. Integ Bin He 4-Byte
25. What kinds of problems are suitable for solution by systolic arrays?
24. Through what metaphor do systolic arrays get their name? Why is the metaphor fairly accurate?
23. Describe how neural networks “learn.”
22. What is the fundamental computing element of a neural network?
20. What differentiates dataflow architectures from “traditional”computational architectures?
12. Explain the limitation inherent in a register-register vector processing architecture.
11. What are the similarities and differences between EPIC and VLIW?
10. In what way does a VLIW design differ from a superpipelined design?
9. How is a superscalar design different from a superpipelined design?
Define superpipelining.
7. Do all programming problems lend themselves to parallel execution? What is the limiting factor?
6. We propose adding a level to Flynn’s taxonomy. What is the distinguishing characteristic of computers at this higher level?
4. Flynn’s taxonomy classifies computer architectures based on two properties. What are they?
3. Describe how register windowing makes procedure calls more efficient.
2. Why is a RISC processor easier to pipeline than a CISC processor?
1. Why was the RISC architecture concept proposed?
Database logs serve two purposes. What are they?
Explain the ACID properties of a database system.
Why are database reorganizations necessary?
Which data structure is most commonly used to index databases?
29. How is a logical database schema different from a physical database schema?
28. What is a magic number that identifies a Java class file?
27. Assemblers produce machine code that is executable after it has been link edited. Java compilers produce __________ that is interpreted during its execution.
26. What is the salient feature of the Java programming language that provides for its portability across disparate hardware environments?
How does an interpreter differ from a compiler?
Describe the purpose of each phase of a compiler.
23. What is the purpose of a link editor? How is it different from a dynamic link library?
22. How does absolute code differ from relocatable code?
21. Describe the programming language hierarchy. Why is a triangle a suitable symbol for representing this hierarchy?
20. Name some advantages of server consolidation. Is server consolidation a good idea for every enterprise?
19. What is the difference between a subsystem and a logical partition?
18. The operating system and a user program hold two different perceptions of a virtual machine. Explain how they differ.
17. What is an overlay? Why are overlays no longer needed in large computer systems?
16. Besides process management, what are the other two important functions of an operating system?
Describe the steps involved in performing a context switch.
Which process scheduling method is provably optimal?
13. Which method of process scheduling is most useful in a timesharing environment?
What is meant by preemptive scheduling?
How is long-term process scheduling different from short-term process scheduling?
What are the benefits and drawbacks to a GUI operating system interface?
Describe the two divergent philosophies concerning operating system kernel design.
What is meant by transparency?
7. How is a distributed operating system different from a networked operating system?
6. Multiprocessor systems can be classified by the way in which they communicate. How are they classified in this chapter?
5. What is the most critical factor in the operation of hard real-time systems?
Describe how multiprogramming systems differ from time-sharing systems.
With regard to printer output, how was the word spool derived?
What improvements to computer operations were brought about by resident monitors?
What was the main objective of early operating systems as compared to the goals of today’s systems?
Give an example of a current stack-based architecture and a current GPR-based architecture. How do they differ?
Explain Java bytecodes.
List several ways in which the Intel and MIPS ISAs differ. Name several ways in which they are the same.
22. Explain superscalar, superpipelining, and VLIW architectures.
21. What are the two types of ILP, and how do they differ?
20. What are the pipeline conflicts that can cause a slowdown in the pipeline?
19. What is the theoretical speedup for a four-stage pipeline with a 20ns clock cycle if it is processing 100 tasks?
18. Explain the concept behind instruction pipelining.
17. Why do we need so many different addressing modes?
16. How does indexed addressing differ from based addressing?
15. Give examples of immediate, direct, register, indirect, register indirect, and indexed addressing.
What is an address mode?
13. Explain what it means for an instruction set to be orthogonal.
12. What is the difference between an arithmetic shift and a logical shift?
11. Name the seven types of data instructions and explain each.
10. Why might stack architectures represent arithmetic expressions in reverse Polish notation?
9. Which is likely to be longer (have more instructions): a program written for a zero-address architecture, a program written for a oneaddress architecture, or a program written for a two-address
8. How does an architecture based on zero operands ever get any data values from memory?
7. What are the pros and cons of fixed-length and variable-length instructions? Which is currently more popular?
6. How do memory-memory, register-memory, and load-store architectures differ? How are they the same?
5. We can design stack architectures, accumulator architectures, or general-purpose register architectures. Explain the differences between these choices and give some situations where one might be
4. If a byte-addressable machine with 32-bit words stores the hex value 98765432, indicate how this value would be stored on a little endian machine and on a big endian machine. Why does
What is an expanding opcode?
2. Several design decisions exist with regard to instruction sets. Name four and explain.
1. Explain the difference between register-to-register, register-tomemory, and memory-to-memory instructions.
12. Data dependencies occur in a pipeline when multiple instructions need the CPU.
11. Resource conflicts occur in a pipeline when there are multiple instructions that require the same resource.

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