Given the following Omega network, which allows eight CPUs

(P0 through P7) to access eight memory modules (M0 through M7):

1.

a) Show how the following connections through the network are achieved (explain how each switch must be set). Refer to the switches as 1A, 2B, etc.:
1. i) P0 → M2 2. ii) P4 → M4 3. iii) P6 → M3 2.

b) Can these connections occur simultaneously, or do they conflict? Explain.
3.

c) List a processor-to-memory access that conflicts (is blocked) by the access P0 → M2 and is not listed in Part (a).
4.

d) List a processor-to-memory access that is not blocked by the access P0 → M2 and is not listed in Part (a).

Transcribed Image Text:

Processor Stage 1 Stage 2 Stage 3 Memory module 000 000 A A A 001 001 010 010 B B B 011 011 100 100 C C 101 101 110 110 D D D 111 111