All Matches
Solution Library
Expert Answer
Textbooks
Search Textbook questions, tutors and Books
Oops, something went wrong!
Change your search query and then try again
Toggle navigation
FREE Trial
S
Books
FREE
Tutors
Study Help
Expert Questions
Accounting
General Management
Mathematics
Finance
Organizational Behaviour
Law
Physics
Operating System
Management Leadership
Sociology
Programming
Marketing
Database
Computer Network
Economics
Textbooks Solutions
Accounting
Managerial Accounting
Management Leadership
Cost Accounting
Statistics
Business Law
Corporate Finance
Finance
Economics
Auditing
Hire a Tutor
AI Tutor
New
Search
Search
Sign In
Register
study help
computer science
essentials of computer organization
Questions and Answers of
Essentials Of Computer Organization
What is the function of a CPU?
If a computer uses hardwired control, the microprogram determines the instruction set for the machine. This instruction set can never be changed unless the architecture is redesigned. True Or False.
What are the main functions of the CPU?
What purpose does a datapath serve?
A branch instruction changes the flow of information by changing the PC. True Or False.
How is the ALU related to the CPU? What are its main functions?
What does the control unit do?
Registers are storage locations within the CPU itself. True Or False.
Explain what the CPU should do when an interrupt occurs. Include in your answer the method the CPU uses to detect an interrupt, how it is handled, and what happens when the interrupt has been
Where are registers located, and what are the different types?
A two-pass assembler generally creates a symbol table during the first pass and finishes the complete translation from assembly language to machine instructions on the second. True Or False.
How many bits would you need to address a 2M × 32 memory if:a. The memory is byte addressable? b. The memory is word addressable?
How does the ALU know which function to perform?
The MAR, MBR, PC, and IR registers in MARIE can be used to hold arbitrary data values. True Or False.
How many bits are required to address a 4M × 16 main memory if: a. Main memory is byte addressable? b. Main memory is word addressable?
Why is a bus often a communications bottleneck?
MARIE has a common bus scheme, which means that a number of entities share the bus. True Or False.
How many bits are required to address a 1M × 8 main memory if:a. Main memory is byte addressable? b. Main memory is word addressable?
What is the difference between a point-to-point bus and a multipoint bus?
An assembler is a program that accepts a symbolic language program and produces the binary machine language equivalent, resulting in a one-to-one correspondence between the assembly language source
Why is a bus protocol important?
If a computer uses microprogrammed control, the microprogram determines the instruction set for the machine. True Or False.
Explain the differences between data buses, address buses, and control buses.
How many 256 × 8 RAM chips are needed to provide a memory capacity of 4096 bytes?a. How many bits will each address contain? b. How many lines must go to each chip? c. How many lines must be
What is a bus cycle?
If memory is 16-way interleaved, it means that memory is implemented using four banks (because 24 = 16 ). True Or False.
Name three different types of buses and where you would find them.
Redo exercise 10 assuming a 16M × 16 memory built using 512 × 8 RAM chips.
What is the difference between synchronous buses and nonsynchronous buses?
What are the four types of bus arbitration?
Explain the difference between clock cycles and clock frequency.
A digital computer has a memory unit with 32 bits per word. The instruction set consists of 110 different operations. All instructions have an operation code part (opcode) and two address fields: one
How do system clocks and bus clocks differ?
What is the function of an I/O interface?
Suppose the RAM for a certain computer has 256M words, where each word is 16 bits long. a. What is the capacity of this memory expressed in bytes? b. If this RAM is byte addressable, how many bits
Explain the difference between memory-mapped I/O and instruction based I/O.
You and a colleague are designing a brand-new microprocessor architecture. Your colleague wants the processor to support 509 different instructions. You do not agree; you would like to have many
Given a memory of 2048 bytes consisting of several 64 × 8 RAM chips, and assuming byte-addressable memory, which of the following seven diagrams indicates the correct way to use the address bits?
What is the difference between a byte and a word? What distinguishes each?
Explain the difference between byte addressable and word addressable.
Explain the steps in the fetch–decode–execute cycle. Your explanation should include what is happening in the various registers.
Why is address alignment important?
List the hexadecimal code for the following program (handassemble it). Hex Address Label 100 101 102 103 104 105 106 107 108 109 S2, S1, A, One, Instruction LOAD A ADD ONE JUMP S1 ADD ONE STORE
List and explain the two types of memory interleaving and the differences between them.
Describe how an interrupt works, and name four different types.
Consider the MARIE program below.a. List the hexadecimal code for each instruction. b. Draw the symbol table. c. What is the value stored in the AC when the program terminates? Hex
How does a maskable interrupt differ from a nonmaskable interrupt?
Given the instruction set for MARIE in this chapter, do the following.Decipher the following MARIE machine language instructions (write the assembly language equivalent): a) 0010000000000111 b)
Explain the functions of all of MARIE’s registers.
Write the assembly language equivalent of the following MARIE machine language instructions: a. 0111000000000000 b. 1011001100110000 C. 0100111101001111
What is an opcode?
Write the assembly language equivalent of the following MARIE machine language instructions: a. 0000010111000000 b. 0001101110010010 c. 1100100101101011
Explain how each instruction in MARIE works.
Write the following code segment in MARIE’s assembly language: if X> 1 then Y = X + X; X = 0; endif; Y = Y + 1;
How does a machine language differ from an assembly language? Is the conversion one-to-one (one assembly instruction equals one machine instruction)?
Write the following code segment in MARIE’s assembly language: if X
What is the significance of RTN?
What are the potential problems (perhaps more than one) with the following assembly language code fragment (implementing a subroutine) written to run on MARIE? The subroutine assumes that the
Is a microoperation the same thing as a machine instruction?
How does a microoperation differ from a regular assembly language instruction?
Write a MARIE program to evaluate the expression A × B × C × D.
Write the following code segment in MARIE assembly language: X = 1; while X < 10 do X = X + endwhile; 1;
Explain the steps of the fetch–decode–execute cycle.
Write the following code segment in MARIE assembly language. Sum = 0; for X = 1 to 10 do Sum Sum + X;
How does interrupt-driven I/O work?
Explain how an assembler works, including how it generates the symbol table, what it does with source and object code, and how it handles labels.
Write a MARIE program using a loop that multiplies two positive numbers by using repeated addition. For example, to multiply 3 × 6, the program would add 3 six times, or 3 + 3 + 3 + 3 + 3 + 3.
Write a MARIE subroutine to subtract two numbers.
What is a stack? Why is it important for programming?
More registers appear to be a good thing, in terms of reducing the total number of memory accesses a program might require. Give an arithmetic example to support this statement. First, determine the
MARIE saves the return address for a subroutine in memory, at a location designated by the JnS instruction. In some architectures, this address is stored in a register, and in many it is stored on a
How does Intel’s architecture differ from MIPS?
Name four Intel processors and four MIPS processors.
Draw the connection of MARIE’s PC to the datapath using the format shown in Figure 4.15. D15 D14 Do *** : Ps P4P3 D Q 4D Q --- 16 D Flip-flops Control unit HD Q P₂ P₁ Po FIGURE 4.15 Connection
Suppose we add the following instruction to MARIE’s ISA: IncSZ Operand This instruction increments the value with effective address “Operand,” and if this newly incremented value is equal to
Suppose some hypothetical system’s control unit has a ring (cycle) counter consisting of some number of D flip-flops. This system runs at 1GHz and has a maximum of 10
Suppose you are designing a hardwired control unit for a very small computerized device. This system is so revolutionary that the system designers have devised an entirely new ISA for it. Because
Draw the timing diagram for MARIE’s Load instruction using the format of Figure 4.16. T3 T5 Po P₁ P₂ Pa РА Ps Ao Cr Ma LALT FIGURE 4.16 Timing Diagram for the Microoperations of MARIE's Add
Building on the idea presented in Exercise 51, suppose that MARIE has a hardwired control unit and we decide to add a new instruction that requires eight clock cycles to execute. (This is one cycle
Draw the timing diagram for MARIE’s Subt instruction using the format of Figure 4.16. T₂ T₂ T₁ Po P₁ P₂ Pa P₁ Ps Ao Gr Ma LALT FIGURE 4.16 Timing Diagram for the Microoperations of
Draw the timing diagram for MARIE’s AddI instruction using the format of Figure 4.16. T₂ TA Ts Po P₁ P₂ Pa PA P6 Au Cr Ma LALT FIGURE 4.16 Timing Diagram for the Microoperations of MARIE's
Using Figure 4.23 as a guide, write the binary microcode for MARIE’s Load instruction. Assume that the microcode begins at instruction line number 01100002. Address 0000000 MAR PC 0000001
Using Figure 4.23 as a guide, write the binary microcode for MARIE’s Add instruction. Assume that the microcode begins at instruction line number 01101002. Address 0000000 MAR← PC 0000001 IR
Which control signals should contain a one for each step in executing the JumpI instruction? Step Fetch RTN MAR+PC IR+M [MAR] PC PC + 1 Decode IR [15-12] Get operand MAR+ IR
Would you recommend a synchronous bus or an asynchronous bus for use between the CPU and the memory? Explain your answer.
Pick an architecture other than those covered in this chapter. Do research to find out how your architecture deals with the concepts introduced in this chapter, as was done for Intel and MIPS.
Which control signals should contain a one for each step in executing the StoreI instruction? Step Fetch Decode IR [15-12] Get operand Execute RTN MARPC IR+M[MAR] PC PC + 1 MARIR
Assume you have a byte-addressable machine that uses 32-bit integers and you are storing the hex value 1234 at address 0a) Show how this is stored on a big endian machine.b) Show how this is stored
True OR False: Most computers typically fall into one of three types of CPU organization: (1) General register organization, (2) Single accumulator organization,(3) Stack organization.
Explain the difference between register-to-register, register-to-memory, and memory-to-memory instructions.
Show how the following values would be stored by byte-addressable machines with 32-bit words, using little endian and then big endian format. Assume that each value starts at address 1016. Draw a
Several design decisions exist with regard to instruction sets. Name four and explain.
Fill in the following table to show how the given integers are represented, assuming that 16 bits are used to store values and the machine uses two’s complement notation
True OR False: An instruction takes less time to execute on a processor using an instruction pipeline than on a processor without an instruction pipeline.
Assume a computer that has 32-bit integers. Show how each of the following values would be stored sequentially in memory, starting at address 0x100, assuming that each address holds 1 byte. Be sure
True OR False: The term “endian” refers to an architecture’s byte ordering.
If a byte-addressable machine with 32-bit words stores the hex value 98765432, indicate how this value would be stored on a little endian machine and on a big endian machine. Why does
True Or False: Stack architectures have good code density and a simple model for evaluation of expressions, but do not allow random access, which can cause a problem with the generation of efficient
We can design stack architectures, accumulator architectures, or general-purpose register architectures. Explain the differences between these choices and give some situations where one might be
True Or False: Most architectures today are accumulator based.
Showing 700 - 800
of 1321
1
2
3
4
5
6
7
8
9
10
11
12
13
14