Design the values of K 1 and K 2 in the system of Figure P7.15 to meet
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Design the values of K1 and K2 in the system of Figure P7.15 to meet the following specifications: Steady-state error component due to a unit step disturbance is -0.00001; steady-state error component due to a unit ramp input is 0.002.
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D(s) R(s) + K(s + 2) K2 C(s) (s +3) s(s +4) FIGURE P7.15
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