An N-bit Johnson counter consists of an N-bit shift register with a reset signal. The output of the shift register (S_out) is inverted and fed back to the input (S_in). When the counter is reset, all of the bits are cleared to 0.

(a) Show the sequence of outputs, Q_3:0, produced by a 4-bit Johnson counter starting immediately after the counter is reset.
(b) How many cycles elapse until an N-bit Johnson counter repeats its sequence? Explain.
(c) Design a decimal counter using a 5-bit Johnson counter, ten AND gates, and inverters. The decimal counter has a clock, a reset, and ten one-hot outputs Y_9:0. When the counter is reset, Y₀ is asserted. On each subsequent cycle, the next output should be asserted. After ten cycles, the counter should repeat. Sketch a schematic of the decimal counter.
(d) What advantages might a Johnson counter have over a conventional counter?