In Verilog

Build a 7-segment display driver that can display a 16-bit input on 47-segment displays in hexdecimal format. (8 pts) Use the shift register module and the block diagram in lab manual to build this. Input: o clk, reset: reset should reset all interal modules in: 16-bit input, they should be displayed on 4 7-segment displays in hexdecimal format. o tick: external counter's tick signal can be fed through this port. Note: There should be an internal counter as well. You can specify which counter to use by a parameter. The selection of internal or external signal should be done in a generator block Output o seg: 7-bit, connect to FPGA's seg o an: 4-bit, connect to FPGA's an To test this module, just connect 16 switches to the input. We will need to use this module next lab Build a 7-segment display driver that can display a 16-bit input on 47-segment displays in hexdecimal format. (8 pts) Use the shift register module and the block diagram in lab manual to build this. Input: o clk, reset: reset should reset all interal modules in: 16-bit input, they should be displayed on 4 7-segment displays in hexdecimal format. o tick: external counter's tick signal can be fed through this port. Note: There should be an internal counter as well. You can specify which counter to use by a parameter. The selection of internal or external signal should be done in a generator block Output o seg: 7-bit, connect to FPGA's seg o an: 4-bit, connect to FPGA's an To test this module, just connect 16 switches to the input. We will need to use this module next lab