Sketch a schematic for a fast 3:8 decoder. Suppose gate delays are given in Table 2.8 (and

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Sketch a schematic for a fast 3:8 decoder. Suppose gate delays are given in Table 2.8 (and only the gates in that table are available). Design your decoder to have the shortest possible critical path, and indicate what that path is. What are its propagation delay and contamination delay?

Table 2.8 Gate delays for Exercises 2.43–2.47 (sd) Pd, 15 Gate ted (ps) NOT 10 15 2-input NAND 20 3-input NAND 30 25 2

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