(a) Assume D 1 = 0, D 2 = 5, and D 1 changes to 1 at...

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(a) Assume D1 = 0, D2 = 5, and Dchanges to 1 at time = 10ns. What are the values of Dand D2 after the following code has been executed once? Do the values of D1 and D2 swap?

always @ (D1)
begin
D2 <= D1;
D1 <= D2;
End
(b) Assume D1 = 0, D2 = 5, and D1 changes to 1 at time = 10 ns. What are the values of D1 and D2 after the following code has been executed once? Do the values
of D1 and D2 swap?
always @ (D1)
begin
D2 = D1;
D1 = D2;
end
(c) How many latches will result when the following code is synthesized? Assume B is 3 bits long.
always @ (State) begin
case(State)
2'b00: B = 5;
2'b01: B = 3;
2'b10: B = 0;
endcase
end

Circle the correct choice:
i. 1 latch because 1 case is missing
ii. 2 latches because state is 2 bits
iii. 3 latches because B is 3 bits
iv. 5 latches because B is 3 bits and state is 2 bits
v. None of the above. But it results in latches.

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Related Book For  book-img-for-question

Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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