Assuming B is driven by the simulator command: force B 0 0, 1 4, 0 10, 1

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Assuming B is driven by the simulator command:
force B 0 0, 1 4, 0 10, 1 15, 0 20, 1 30, 0 40
Draw a timing diagram illustrating A, B, and C if the following concurrent statements are executed:
always @(B)
begin
A <= #5 B;
end
assign
#5 C <= B;

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Related Book For  book-img-for-question

Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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