Question: For the floating-point adder of Figure 7-14, modify the Verilog code so that (a) It handles IEEE standard single precision denormalized numbers both as input

For the floating-point adder of Figure 7-14, modify the Verilog code so that
(a) It handles IEEE standard single precision denormalized numbers both as input and output.
(b) In state 2, it speeds up the processing when the exponents differ by more than 23.
(c) It rounds up instead of truncating the resulting fraction.

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