Given the following timing waveform for Y, draw D and E. wire #4 D; // net delay

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Given the following timing waveform for Y, draw D and E.

13ns 5ns i 10ns | 10ns 2 ns 10 30 40 50 20

wire #4 D; // net delay on wire D
assign #6 D = Y; // statement 1 2 inertial delay
wire #6 E; // net delay on wire E
assign #4 E = Y; // statement 1 - inertial delay

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Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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