Given Z(T, U, V, W, X, Y) = VW'X + U'V'WY + TV'WY',

(a) Show how Z can be realized using a single Figure 6-3 logic block. Show the cell inputs on a copy of Figure 6-3; indicate the internal connections in the cell; and specify the functions X, Y, and Z.

Figure 6-3

(b) Show how Z can be realized using two Figure 6-1(a) logic blocks. Draw a diagram showing the inputs to each cell, the interconnections between cells, and the X and Y functions for each cell.

Figure 6-1(a)

Transcribed Image Text:

х, CE FF X2 X Function Xout | X, generator Z Function LUT4 | X4 generator LUT3 QY Y1 CE | Y2 Y Function generator Y3 LUT4 Y4 Yout Figure 6-3 Programmable MUX