Add inverted outputs to the HDL NAND latch designs given in Figure 5-76 or Figure 5-77. Verify
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Add inverted outputs to the HDL NAND latch designs given in Figure 5-76 or Figure 5-77. Verify correct operation by simulation.
Figure 5-76
Figure 5-77
Transcribed Image Text:
SUBDESIGN fig5_76 sbar, rbar 9 ( ) BEGIN END; IF sbar 0 ELSIF rbar -- 0 ELSE END IF; :INPUT; :OUTPUT; THEN q vcc; THEN q- GND; q-q; set or illegal command reset hold
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Related Book For
Digital Systems Principles And Application
ISBN: 9780134220130
12th Edition
Authors: Ronald Tocci, Neal Widmer, Gregory Moss
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