Simulate the HDL design for a NAND latch given in Figure 5-76 (AHDL) or Figure 5-77 (VHDL).

Question:

Simulate the HDL design for a NAND latch given in Figure 5-76 (AHDL) or Figure 5-77 (VHDL). What does this S-R latch do if an “invalid” input command is applied? Since we know that any S-R latch can have an unusual output result when an invalid input command is applied, you should simulate that input condition as well as the latch’s normal set, reset, and hold commands. Some latch designs can have a tendency for the output to oscillate when an invalid command is followed by a hold command, so be sure to check for that in your simulation.


Figure 5-76

SUBDESIGN fig5_76 sbar, rbar 9 ( ) BEGIN END; IF sbar 0 ELSIF rbar -- 0 ELSE END IF; :INPUT; :OUTPUT; THEN q


Figure 5-77

ENTITY fig5 77 IS PORT (sbar, rbar q END fig5_77; ARCHITECTURE behavior OF fig5_77 IS BEGIN PROCESS (sbar,

Fantastic news! We've Found the answer you've been seeking!

Step by Step Answer:

Related Book For  book-img-for-question

Digital Systems Principles And Application

ISBN: 9780134220130

12th Edition

Authors: Ronald Tocci, Neal Widmer, Gregory Moss

Question Posted: