Consider the design of a circuit that controls the traffic lights at the intersection of two roads. The circuit generates the outputs G1, Y 1, R1 and G2, Y 2, R2. These outputs represent the states of the green, yellow, and red lights, respectively, on each road. A light is turned on if the corresponding output signal has the value 1. The lights have to be controlled in the following manner: when G1 is turned on it must remain on for a time period called t₁ and then be turned off. Turning off G1 must result in Y1 being immediately turned on; it should remain on for a time period called t₂ and then be turned off. When either G1 or Y1 is on, R2 must be on and G2 and Y2 must be off. Turning off Y1 must result in G2 being immediately turned on for the t₁ time period. When G2 is turned off, Y 2 is turned on for the t₂ time period. Of course, when either G2 or Y 2 is turned on, R1 must be turned on and G1 and Y1 must be off.

(a) Give an ASM chart that describes the traffic-light controller. Assume that two down counters exist, one that is used to measure the t₁ delay and another that is used to measure t₂. Each counter has parallel-load and enable inputs. These inputs are used to load an appropriate value representing either the t₁ or t₂ delay and then allow the counter to count down to 0.

(b) Give an ASM chart for the control circuit for the traffic-light controller.

(c)Write complete Verilog code for the traffic-light controller, including the control circuit from part (a) and counters to represent t₁ and t₂. Use any convenient clock frequency to clock the circuit and assume convenient count values to represent t₁ and t₂. Give simulation results that illustrate the operation of your circuit.