The circuit in Figure P11.5 determines the parity of a four-bit data unit. Derive a minimal test
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The circuit in Figure P11.5 determines the parity of a four-bit data unit. Derive a minimal test set that can detect all single stuck-at-0 and stuck-at-1 faults in this circuit. Would your test set work if the XOR gates are implemented using the circuit in Figure 8.9c? Can your result be extended to a general case that involves n-bit data units?
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a I can say that a stuckatone fault occurs only at one flipflop FF in this circuit So ...View the full answer
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Related Book For 
Fundamentals Of Digital Logic With Verilog Design
ISBN: 9780073380544
3rd Edition
Authors: Stephen Brown, Zvonko Vranesic
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