A serial leading- 1s detector is to be designed. A binary integer of arbitrary length is presented to the serial leading- 1s detector, most significant bit first, on input X. When a given bit is presented on input X, the corresponding output bit is to appear during the same clock cycle on output Z. As long as the bits applied to X are 0, Z = 0. When the first 1 is applied to X, Z = 1. For all bit values applied to X after the first 1 is applied, Z = 0. To indicate that a sequence is complete and that the circuit is to be initialized to receive another sequence, input Y becomes 1 for one clock cycle. Otherwise, Y is 0.

(a) Find the state diagram for the serial leading- 1s detector.

(b) Find the state table for the serial leading- 1s detector.