For each of the RISC operations in Table 10-1, list the addressing mode or modes used.

Table 10-1

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Operation No Operation Move A Add Subtract AND OR Exclusive-OR Complement Add Immediate Subtract Immediate AND Immediate OR Immediate Exclusive-OR Immediate Symbolic Notation Opcode Action NOP 0000000 None MOVA 1000000 R[DR] ADD 0000010 R[DR] SUB 0000101 R[DR] AND OR Branch if Zero Branch if Nonzero XOR NOT Add Immediate Unsigned Subtract Immediate SIU Unsigned Move B MOVB Logical Right Shift by LSR SH Bits Jump Jump and Link ADI SBI ANI ORI XRI Logical Left Shift by LSL SH Bits AIU Logical Left Shift by LSL SH Bits Load Store Jump Register Set if Less Than LD ST JMR SLT BZ BNZ JMP JML 0001000 0001001 R[DR] R[SA] ^ R[SB] R[DR] 0001010 R[DR] R[SA] 0001011 R[DR] R[SA] 0100010 R[DR] R[SA] + 0100101 R[DR] R[SA] 0101000 R[DR] R[SA] ^ (0 || IM) 0101001 R[DR] R[SA] V (0 || IM) 0101010 R[DR] R[SA] (0 || IM) 1000010 R[DR] 1000101 R[DR] 0001100 0001101 0001110 0001110 0010000 0100000 R[SA] R[SA] + R[SB] R[SA] + R[SB] + 1 R[SA] V R[SB] R[SB] 1100101 1100000 1001000 If R[SA] 1101000 PC- 0110000 PC R[SA] + (0 || IM) R[SA] + (0|IM) + 1 R[DR] R[SB] R[DR] - Isr R[SA] by SH R[DR] -Isl R[SA] by SH R[DR] Isl R[SA] by SH R[DR] M[R[SA]] M[R[SA]] R[SB] se IM (se IM) + 1 1110000 PC - R[SA] If R[SA] < R[SB] then R[DR] = 1 If R[SA] = 0, then PC PC + 1+ se IM 0, then PC - PC + 1+ se IM PC + 1+ se IM PC + 1 + se IM, R[DR] PC + 1