Assume that a bus transfer takes T seconds and memory access time is 47 seconds. A read request over a conventional bus then requires 67 seconds to complete. How many conventional buses are needed to equal or exceed the bandwidth of a split- transaction bus that operates with the same time delays? Consider only read requests, ignore memory conflicts, and assume that all memory modules are connected to all buses in the multiple bus case. Does your answer increase or decrease if memory access time increases?