10. A direct-mapped cache is at one extreme of cache designs, with set-associative caches in the middle. At the opposite extreme is the fully associative cache, where there is in essence only one entry in the cache of Figure 12.29(a), and the Line field of the address has zero bits

—that is, it is missing altogether. An address consists of only the Tag field and the Byte field.

(a) In Figure 12.29, instead of having 8 cache cells, each with 4 lines, you could use the same number of bits with 1 cache cell having 32 lines. Would this design increase the cache hit percentage over that in Figure 12.29? Explain.

(b) How many comparators in the read circuit would be required for the cache of part (a)?