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0070316228 5. According to program order, the following six arithmetic expressions need to be exccuted in minimum time. Assume that all integer operands are al-

0070316228
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5. According to program order, the following six arithmetic expressions need to be exccuted in minimum time. Assume that all integer operands are al- ready loaded into working registers. No memory reference is needed for the operand fetch. Also, all intermediate or final results are written back to working registers without conflicts PI: P2: X(A+B)(A-B) Y (C + D)/(C-D) (a) Use the minimum number of working registers to rewrite the above HLL program into a minimum length assembly language code us- ing arithmetic opcodes add, subtract, multiply and divide exclusivel Assume a fixed instruction format with three register fields: two for sources and one for destinations: opcode D, S1, S2. (b) Perform a flow analysis of the assembly code obtained in part (a) to reveal all data dependences with a dependence graph. (c) The CPU is assumed to have two add units, one multiply unit and one divide unit. Work out an optimal schedule to execute the assembl code in minimum time, assuming 1 cycle for the add unit, 3 cycles for the multiply unit, and 18 cycles for the divide unit to complete the execution of one instruction. Ignore all overhead caused by instruction fetch, decode, and writeback. 5. According to program order, the following six arithmetic expressions need to be exccuted in minimum time. Assume that all integer operands are al- ready loaded into working registers. No memory reference is needed for the operand fetch. Also, all intermediate or final results are written back to working registers without conflicts PI: P2: X(A+B)(A-B) Y (C + D)/(C-D) (a) Use the minimum number of working registers to rewrite the above HLL program into a minimum length assembly language code us- ing arithmetic opcodes add, subtract, multiply and divide exclusivel Assume a fixed instruction format with three register fields: two for sources and one for destinations: opcode D, S1, S2. (b) Perform a flow analysis of the assembly code obtained in part (a) to reveal all data dependences with a dependence graph. (c) The CPU is assumed to have two add units, one multiply unit and one divide unit. Work out an optimal schedule to execute the assembl code in minimum time, assuming 1 cycle for the add unit, 3 cycles for the multiply unit, and 18 cycles for the divide unit to complete the execution of one instruction. Ignore all overhead caused by instruction fetch, decode, and writeback

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