02: Problem: Design and Simulation of 8-bit ALU Design ansit ALU circuit that receives two input numbers X7101 and Y1710). and produces bit output 17:01, an output carry out, an overflow frago, and to flag The circuit Implements the following 12 functions based on a control input 13:01 Code Function 000 Addition *** 001 SUKONEXO 010 Reminder 011 Bowie AND EXAY 100 Bitwisely 101 Conce-X15:01 102 110 Equality 111 Less than out- Notes: Show the block diagram design of your bt ALU using componentske Adder Milor, etc. as needed Model each component separately. You should have different modules for the adder multiplexer etc Write a Verlog test scenarios to test both the ALU Verify the correctness by simulation Show snapshots of tion wiveforms Submit a report (Word or Pos document should contain Problem description, the block diagram, a copy of the worlog modules and the waveforms taken directly as snapshots from the simulator In addition to building the Quartus project, you need to write down one report for each student that includes the following items 1. System Design 2. Verilog code 3. Simulation results