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(1) A 5-stage pipeline has a single unified instruction and data memory capable of performing a single Read or Write operation every clock cycle. Assume that 18% of the executed instructions are Loads and 12% are Store. Ignoring any data hazards and control hazards that may occur, what is the speedup of the pipeline that has separate instruction and data memories over the pipeline with a single unified memory?

(2). A 5-stage pipeline has a Register File that can execute either a Read operation (of 1 or 2 registers) or a Write operation (into only one register), but not both, during every clock cycle. The instruction mix that the processor executes contains 47% ALU instructions,24% Load, 11% Store and 18% Branch. Ignoring any data hazards and control hazards that may occur, what is the speedup of the pipeline that has a Register File capable of performing two reads and one write every cycle over the pipeline with the limited Register file?