1. (5 points) Design a 4-bit carry-look-ahead adder (1-level of CLA). Make sure to show the design of the basic block used in the adder (i.e. FA with carry logic removed) as well as the logic that generates all carries (CLA logic). Give the delay of each output signal in the unit assuming that the delay of any gate is rtmma regardless of its type where "n" is the ceiling function. For example, a five input AND gate has a delay of [1.67]