Consider the following FICO pipeline: IF DISP EX' WB Assumptions EX takes 2 (pipelined) cycles for LW, and 1 cycle for ADD There is only one ADD unit and one LW unit Fetch width = 2. * The DISP queue is unlimited in length When an instruction completes and clears the busy bit on its destination register, any instruction waiting in DISP for that register can fire in the same cycle. A. LW R1,0(R2) B. ADD R3,R1,R2 C. ADD R5,R4,R2 D. LW R6,0(R4) E. ADD R7,R1,R5 F. ADD R8,R6,R3 This sequence executed on an out-of-order processor that has 6 LW units and 6 ADD units. LW is pipelined into 2 cycles, ADD is a single-cycle operation. The fetch width is now 6 instructions/cycle. Show the contents of the scheing queue and the register file at two snapshots in time: a) after all 6 instructions have been dispatched. b) after instructions A, C and D have completed Assume Tmauletags begin at the value 100. Value fields are ignored for the purposes of this question Consider the following FICO pipeline: IF DISP EX' WB Assumptions EX takes 2 (pipelined) cycles for LW, and 1 cycle for ADD There is only one ADD unit and one LW unit Fetch width = 2. * The DISP queue is unlimited in length When an instruction completes and clears the busy bit on its destination register, any instruction waiting in DISP for that register can fire in the same cycle. A. LW R1,0(R2) B. ADD R3,R1,R2 C. ADD R5,R4,R2 D. LW R6,0(R4) E. ADD R7,R1,R5 F. ADD R8,R6,R3 This sequence executed on an out-of-order processor that has 6 LW units and 6 ADD units. LW is pipelined into 2 cycles, ADD is a single-cycle operation. The fetch width is now 6 instructions/cycle. Show the contents of the scheing queue and the register file at two snapshots in time: a) after all 6 instructions have been dispatched. b) after instructions A, C and D have completed Assume Tmauletags begin at the value 100. Value fields are ignored for the purposes of this