1. An IBM PowerPC L1 cache has 128 sets. It adopts 4-way set associative organization with 16-byte cache blocks. What is the cache size?

2. A cache contains 4K blocks and each block contains 16 words. What is the number of sets and the total number of tag bits if the cache is (1) direct-mapped, (2) two-way set associative, and (3) fully associative.

3. A processor is running a program with 30% of load and store instructions; The instruction cache miss rate is 3%; The data cache miss rate is 2%; The processor has a CPI=1.0 without memory stalls; The miss penalty is 50ns for all misses; Assuming CPU frequency is 2GHz. How much faster would the processors run with a perfect cache that has no misses?

4. If a 10-CPU computer need to finish the following two computations:

(1) add 10 numbers together (not parallel computing)

(2) add two matrices, each is 10X10 (parallel computing)

What is the speed up if we increase the number of CPU from 10 to 50?

Please provide answers with proper explaination. Thank you.